Design and FPGA Implementation of a Quantized YOLO Accelerator for Low-Latency Edge Object Detection

Abstract

Real-time object detection on edge devices is challenging because such platforms must deliver low inference latency and high throughput under tight hardware-resource and power budgets. This work presents the design and field-programmable gate array (FPGA) implementation of a quantized YOLO (You Only Look Once) accelerator for edge object detection. The proposed approach combines a YOLO-based detection model with reduced arithmetic precision, parallel processing, pipelining, and memory-efficient dataflow to improve inference efficiency. Model quantization lowers the memory footprint and computational demand of the detector while limiting accuracy loss, and the FPGA architecture is optimized to accelerate computationally intensive operations such as convolution. The accelerator is evaluated in terms of mean average precision (mAP), precision, recall, inference latency, throughput, FPGA resource utilization, power consumption, and energy per inference, and it is compared with the corresponding floating-point and quantized software models. In the measured comparison, the accelerator that is proposed achieves the highest across both latency, throughput and power and energy efficiency in technical data collected while maintaining a detection accuracy that reaches 91% instead of 93% that the floating point approach achieves. The results demonstrate that it is possible to utilize quantization with the parallel, pipelined architectural approach based on FPGA in order to significantly lower cost of YOLO inferences executed on edge devices with very little accuracy decrease.