Variable-to-Variable Run Length Encoding Technique for Testing Low Power VLSI Circuits

Abstract

Enhancing the integration capability in semiconductor technology requires a large amount of test data, resulting in higher memory, time for transition and time for testing. A novel lossless data compression technique is proposed in this paper to reduce test data, time and memory based on the encoding scheme factor to variable run size. A test data are partitioned into variable length test patterns in this scheme and the bits are compressed into variable length codes by applying the compression algorithm. With a limited number of code words, the encoding technique enhances the reduction of test data. The compression technique is effective, especially when the 0s and 1s runs in the test set are high and compress the data streams composed of 0's and 1's runs efficiently. The variable to variable run length code algorithm is used to make changes to test vectors and can be adapted to compress pre-computed test sets to test system-on-chip (SOC) embedded cores.