A 5- GHz CMOS Low Noise Amplifier with High Gain and Low Power using Pre-distortion Technique

Abstract

In this paper, a linearization technique called Pre-distortion is proposed with low noise amplifier and the design was implemented in 90- nm CMOS process. In this proposed design, pre-distortion circuit is employed in front of the low noise amplifier, which comprises of current reuse structure with source follower at the feedback reduces the power dissipation at the transmitter side of the amplifier. Pre-distorter line arizer improves the overall power efficiency of the LNA, with which high gain and low power is achieved. This proposed architecture supports the frequency of 5-GHz suitable for multiband standards with the wireless receivers applications. At 5-GHZ frequency it achieves high gain of 25 dB with low NF of 1.0 dB and power gain (S₂₁) of 27.64 Db is obtained with good matching at input (S₁₁)< - 10bB, which consumes low power of 5nW with efficient power at supply voltage of 3.3V.