Implementations of Artificial Intelligence for Automated Electrical Design in Integrated Circuits

Abstract

In this paper, we propose a unique approach that uses information set to automatically create a trained-classifier integrated circuit. A dataset in comma-separated value format is accepted by the framework, which then goes through several processing processes to produce a trained model. Once the model has been created, the framework produces a tree-based ML classifier in Verilog and XML. We display the structure of the created graph using the XML participation, and we express the trained model using the Verilog code as an electronic specification tool. In our framework, a Field Programmable Gate Array (FPGA) design validation flow receives the Verilog code as input. A customized classifier integrated circuit is then constructed, and the Application Specific Integrated Circuit (ASIC) flow implementation is automated. When addressing the implementation of ML classifiers, the suggested framework's originality is in bridging the gap between the training of ML models and their hardware design. The design automation and deployment of bespoke ML classifier chips from raw dataset files provide several issues our approach tackles. In this paper, we address these issues in depth and describe how researchers can use our suggested methodology to create classifier chips with cheap costs and great performance. With an average multiplication accuracy of 80.79% throughout several distinct information sets, our algorithm runs at hundred MHZ.