Performance optimization on System on Chip using I²C Concept 6G Computer

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D.Kanimozhi
P.Karthikeyan
S.Kirthika

Abstract

In this paper we deliberated the delay reduction in multi core processor on soc to perform multi tasking by means of I2C concept and controlled cache memory. To embed multiple applications on the CHIP, control the process execution. In that we are using EHCI (Embedded Host Controller interface) to communicate outside peripherals to chip. The special concept disused dual mode of operation active and sleep mode .To execute overall system operation by means of embedded OS.

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How to Cite
D.Kanimozhi, P.Karthikeyan, & S.Kirthika. (2022). Performance optimization on System on Chip using I²C Concept 6G Computer. IIRJET, 1(4). https://doi.org/10.32595/iirjet.org/v1i4.2016.20 (Original work published June 7, 2022)